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DS1230Y/ab 256k nonvolatile sram DS1230Y/ab 042398 1/12 features ? 10 years minimum data retention in the absence of external power ? data is automatically protected during power loss ? replaces 32k x 8 volatile static ram, eeprom or flash memory ? unlimited write cycles ? lowpower cmos ? read and write access times as fast as 70 ns ? lithium energy source is electrically disconnected to retain freshness until power is applied for the first time ? full 10% v cc operating range (DS1230Y) ? optional 5% v cc operating range (ds1230ab) ? optional industrial temperature range of 40 c to +85 c, designated ind ? jedec standard 28pin dip package ? new powercap module (pcm) package directly surfacemountable module replaceable snapon powercap provides lith- ium backup battery standardized pinout for all nonvolatile sram products detachment feature on powercap allows easy removal using a regular screwdriver pin assignment oe ce we v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 34 33 32 31 30 29 28 27 26 25 24 23 22 14 15 16 17 21 20 19 18 nc nc a14 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 nc dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd nc nc nc gnd v bat 34pin powercap module (pcm) (uses ds9034pc powercap) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 dq0 dq1 dq2 gnd v cc we a13 a8 a9 a11 oe a10 ce dq7 dq6 dq5 dq4 dq3 28pin encapsulated package 740 mil extended pin description a0 a14 address inputs dq0 dq7 data in/data out ce chip enable we write enable oe output enable v cc power (+5v) gnd ground nc no connect
DS1230Y/ab 042398 2/12 description the ds1230 256k nonvolatile srams are 262,144bit, fully static, nonvolatile srams organized as 32,768 words by 8 bits. each nv sram has a selfcontained lithium energy source and control circuitry which con- stantly monitors v cc for an outoftolerance condition. when such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. dip-package ds1230 devices can be used in place of existing 32k x 8 static rams directly conforming to the popular bytewide 28pin dip standard. the dip devices also match the pinout of 28256 eeproms, al- lowing direct substitution while enhancing performance. ds1230 devices in the low profile module package are specifically designed for surfacemount applications. there is no limit on the number of write cycles that can be executed and no additional support circuitry is re- quired for microprocessor interfacing. read mode the ds1230 devices execute a read cycle whenever we (write enable) is inactive (high) and ce (chip en- able) and oe (output enable) are active (low). the unique address specified by the 15 address inputs (a 0 - a 14 ) defines which of the 32,768 bytes of data is to be accessed. valid data will be available to the eight data output drivers within t acc (access time) after the last address input signal is stable, providing that ce and oe (output enable) access times are also satisfied. if oe and ce access times are not satisfied, then data access must be measured from the later occurring signal (ce or oe ) and the limiting parameter is either t co for ce or t oe for oe rather than address access. write mode the ds1230 devices execute a write cycle whenever the we and ce signals are active (low) after address in- puts are stable. the later occurring falling edge of ce or we will determine the start of the write cycle. the write cycle is terminated by the earlier rising edge of ce or we . all address inputs must be kept valid throughout the write cycle. we must return to the high state for a minimum recovery time (t wr ) before another cycle can be initiated. the oe control signal should be kept inac- tive (high) during write cycles to avoid bus contention. however, if the output drivers are enabled (ce and oe active) then we will disable the outputs in t odw from its falling edge. data retention mode the ds1230ab provides full functional capability for v cc greater than 4.75 volts and write protects by 4.5 volts. the DS1230Y provides full functional capability for v cc greater than 4.5 volts and write protects by 4.25 volts. data is maintained in the absence of v cc without any additional support circuitry. the nonvolatile static rams constantly monitor v cc . should the supply volt- age decay, the nv srams automatically write protect themselves, all inputs become adon't care,o and all out- puts become high impedance. as v cc falls below ap- proximately 3.0 volts, a power switching circuit con- nects the lithium energy source to ram to retain data. during powerup, when v cc rises above approximately 3.0 volts, the power switching circuit connects external v cc to ram and disconnects the lithium energy source. normal ram operation can resume after v cc exceeds 4.75 volts for the ds1230ab and 4.5 volts for the DS1230Y. freshness seal each ds1230 device is shipped from dallas semicon- ductor with its lithium energy source disconnected, guaranteeing full energy capacity. when v cc is first applied at a level greater than 4.25 volts, the lithium en- ergy source is enabled for battery backup operation. packages the ds1230 devices are available in two packages: 28pin dip and 34pin powercap module (pcm). the 28pin dip integrates a lithium battery, an sram memory and a nonvolatile control function into a single package with a jedecstandard 600 mil dip pinout. the 34pin powercap module integrates sram memory and nonvolatile control along with contacts for connection to the lithium battery in the ds9034pc pow- ercap. the powercap module package design allows a ds1230 pcm device to be surface mounted without subjecting its lithium backup battery to destructive high temperature reflow soldering. after a ds1230 pcm is reflow soldered, a ds9034pc powercap is snapped on top of the pcm to form a complete nonvolatile sram module. the ds9034pc is keyed to prevent improper attachment. ds1230 powercap modules and ds9034pc powercaps are ordered separately and shipped in separate containers. see the ds9034pc data sheet for further information.
DS1230Y/ab 042398 3/12 absolute maximum ratings* voltage on any pin relative to ground 0.3v to +7.0v operating temperature 0 c to 70 c, 40 c to +85 c for ind parts storage temperature 40 c to +70 c, 40 c to +85 c for ind parts soldering temperature 260 c for 10 seconds * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (t a : see note 10) parameter symbol min typ max units notes ds1230ab power supply voltage v cc 4.75 5.0 5.25 v DS1230Y power supply voltage v cc 4.5 5.0 5.5 v logic 1 v ih 2.2 v cc v logic 0 v il 0.0 0.8 v (v cc =5v 5% for ds1230ab) dc electrical characteristics (t a : see note 10) (v cc =5v 10% for DS1230Y) parameter symbol min typ max units notes input leakage current i il 1.0 +1.0 m a i/o leakage current ce v ih v cc i io 1.0 +1.0 m a output current @ 2.4v i oh 1.0 ma output current @ 0.4v i ol 2.0 ma standby current ce = 2.2v i ccs1 5.0 10.0 ma standby current ce = v cc -0.5v i ccs2 3.0 5.0 ma operating current i cco1 85 ma write protection voltage (ds1230ab) v tp 4.50 4.62 4.75 v write protection voltage (DS1230Y) v tp 4.25 4.37 4.5 v capacitance (t a = 25 c) parameter symbol min typ max units notes input capacitance c in 5 10 pf input/output capacitance c i/o 5 10 pf
DS1230Y/ab 042398 4/12 (v cc =5v 5% for ds1230ab) ac electrical characteristics (t a : see note 10) (v cc =5v 10% for DS1230Y) parameter symbol ds1230ab-70 DS1230Y-70 ds1230ab-85 DS1230Y-85 ds1230ab-100 DS1230Y-100 units notes parameter symbol min max min max min max units notes read cycle time t rc 70 85 100 ns access time t acc 70 85 100 ns oe to output valid t oe 35 45 50 ns ce to output valid t co 70 85 100 ns oe or ce to output active t coe 5 5 5 ns 5 output high z from dese- lection t od 25 30 35 ns 5 output hold from address change t oh 5 5 5 ns write cycle time t wc 70 85 100 ns write pulse width t wp 55 65 75 ns 3 address setup time t aw 0 0 0 ns write recovery time t wr1 t wr2 5 15 5 15 5 15 ns 12 13 output high z from we t odw 25 30 35 ns 5 output active from we t oew 5 5 5 ns 5 data setup time t ds 30 35 40 ns 4 data hold time t dh1 t dh2 0 10 0 10 0 10 ns 12 13
DS1230Y/ab 042398 5/12 ac electrical characteristics (cont'd) parameter symbol ds1230ab-120 DS1230Y-120 ds1230ab-150 DS1230Y-150 ds1230ab-200 DS1230Y-200 units notes parameter symbol min max min max min max units notes read cycle time t rc 120 150 200 ns access time t acc 120 150 200 ns oe to output valid t oe 60 70 100 ns ce to output valid t co 120 150 200 ns oe or ce to output ac- tive t coe 5 5 5 ns 5 output high z from dese- lection t od 35 35 35 ns 5 output hold from address change t oh 5 5 5 ns write cycle time t wc 120 150 200 ns write pulse width t wp 90 100 100 ns 3 address setup time t aw 0 0 0 ns write recovery time t wr1 t wr2 5 15 5 15 5 15 ns 12 13 output high z from we t odw 35 35 35 ns 5 output active from we t oew 5 5 5 ns 5 data setup time t ds 50 60 80 ns 4 data hold time t dh1 t dh2 0 10 0 10 0 10 ns 12 13
DS1230Y/ab 042398 6/12 read cycle t rc t acc v ih v il v ih v il v ih v il t oh v ih t od t od v ih v oh v ol v oh v ol t coe t coe output data valid d out oe addresses v ih v ih t oe v il v il ce t co see note 1 write cycle 1 t wc v ih v il v ih v il v ih v il addresses t aw data in stable high impedance v il v il v il v il v ih v ih t wp t wr1 t odw t oew t ds t dh1 v ih v il v ih v il ce we d out d in see notes 2, 3, 4, 6, 7, 8 and 12
DS1230Y/ab 042398 7/12 write cycle 2 t wc v il v ih v il v ih v il v ih addresses ce we d out d in data in stable t aw t wp t wr2 v ih v il v il v il v ih v ih v il v il t coe t odw t ds t dh2 v il v ih v il v ih see notes 2, 3, 4, 6, 7, 8 and 13 powerdown/powerup condition v cc 3.2v t f t pd t r t rec data retention time t dr leakage current i l supplied from lithium cell ce v tp see note 11
DS1230Y/ab 042398 8/12 powerdown/powerup timing (t a : see note 10) parameter symbol min typ max units notes ce, at v ih before powerdown t pd 0 m s 11 v cc slew from v tp to 0v (ce at v ih ) t f 300 m s v cc slew from 0v to v tp (ce at v ih ) t r 300 m s ce, at v ih after power-up t rec 2 125 ms (t a = 25 c) parameter symbol min typ max units notes expected data retention time t dr 10 years 9 warning: under no circumstance are negative undershoots, of any amplitude, allowed when device is in battery backup mode. notes: 1. we is high for a read cycle. 2. oe = v ih or v il . if oe = v ih during write cycle, the output buffers remain in a high impedance state. 3. t wp is specified as the logical and of ce and we . t wp is measured from the latter of ce or we going low to the earlier of ce or we going high. 4. t dh , t ds are measured from the earlier of ce or we going high. 5. these parameters are sampled with a 5 pf load and are not 100% tested. 6. if the ce low transition occurs simultaneously with or latter than the we low transition, the output buffers remain in a high impedance state during this period. 7. if the ce high transition occurs prior to or simultaneously with the we high transition, the output buffers remain in high impedance state during this period. 8. if we is low or the we low transition occurs prior to or simultaneously with the ce low transition, the output buffers remain in a high impedance state during this period. 9. each DS1230Y has a builtin switch that disconnects the lithium source until v cc is first applied by the user. the expected t dr is defined as accumulative time in the absence of v cc starting from the time power is first applied by the user. 10. all ac and dc electrical characteristics are valid over the full operating temperature range. for commercial prod- ucts, this range is 0 c to 70 c. for industrial products (ind), this range is 40 c to +85 c. 11. in a power down condition the voltage on any pin may not exceed the voltage on v cc . 12. t wr1 and t dh1 are measured from we going high. 13. t wr2 and t dh2 are measured from ce going high. 14. ds1230 dip modules are recognized by underwriters laboratory (u.l. ? ) under file e99151. ds1230 powercap modules are pending u.l. review. contact the factory for status.
DS1230Y/ab 042398 9/12 dc test conditions outputs open cycle = 200 ns for operating current all voltages are referenced to ground ac test conditions output load: 100 pf + 1ttl gate input pulse levels: 0 3.0v timing measurement reference levels input: 1.5v output: 1.5v input pulse rise and fall times: 5 ns ordering information ds1230 ttp sss iii operating temperature range blank: 0 to 70 ind: 40 to 85 c access 70: 85: 100: 120: 150: 200: speed 70 ns 85 ns 100 ns 120 ns 150 ns 200 ns v cc tolerance ab: 5% y: 10% package type blank: 28pin 600 mil dip p: 34pin powercap module DS1230Y/ab nonvolatile sram, 28pin 740 mil extended dip module a 1 dim min max a in. mm b in. mm c in. mm d in. mm e in. mm f in. mm g in. mm h in. mm j in. mm k in. mm 1.480 37.60 1.500 38.10 0.720 18.29 0.740 18.80 0.355 9.02 0.375 9.52 0.080 2.03 0.110 2.79 0.015 0.38 0.025 0.63 0.120 3.05 0.160 4.06 0.090 2.29 0.110 2.79 0.590 14.99 0.630 16.00 0.008 0.20 0.012 0.30 0.015 0.38 0.021 0.53 c f g k d h b e j 28pin pkg
DS1230Y/ab 042398 10/12 DS1230Y/ab nonvolatile sram, 34pin powercap module pkg dim inches min nom max a 0.920 0.925 0.930 b 0.980 0.985 0.990 c 0.080 d 0.052 0.055 0.058 e 0.048 0.050 0.052 f 0.015 0.020 0.025 g 0.020 0.025 0.030 top view side view bottom view: reference only components and placements may differ from those shown
DS1230Y/ab 042398 11/12 DS1230Y/ab nonvolatile sram, 34pin powercap module with powercap pkg dim inches min nom max a 0.920 0.925 0.930 b 0.955 0.960 0.965 c 0.240 0.245 0.250 d 0.052 0.055 0.058 e 0.048 0.050 0.052 f 0.015 0.020 0.025 g 0.020 0.025 0.030 top view side view bottom view: reference only components and placements may differ from those shown assembly and use reflow soldering dallas semiconductor recommends that powercap module bases experience one pass through solder reflow oriented labelside up (livebug). hand soldering and touchup do not touch soldering iron to leads for more than 3 seconds. to solder, apply flux to the pad, heat the lead frame pad and apply solder. to remove part, apply flux, heat pad until solder reflows, and use a solder wick. lpm replacement in a socket to replace a low profile module in a 68pin plcc socket, attach a ds9034pc powercap to a module base then insert the complete module into the socket one row of leads at a time, push- ing only on the corners of the cap. never apply force to the center of the device. to remove from a socket, use a plcc extraction tool and ensure that it does not hit or damage any of the module ic components. do not use any other tool for extraction.
DS1230Y/ab 042398 12/12 recommended powercap module land pattern pkg dim inches min nom max a 1.050 b 0.826 c 0.050 d 0.030 e 0.112 a d b c e 16 pl recommended powercap module solder stencil pkg dim inches min nom max a 1.050 b 0.890 c 0.050 d 0.030 e 0.080 a d b c e 16 pl

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